The present invention relates generally to integrated circuits and relates more specifically to metal patterning processes for use in manufacturing integrated circuits.
Integrated circuits commonly use metal interconnects (or “lines”) to connect transistors and other semiconductor devices on the ICs. These interconnects are typically fabricated during back end of line (BEOL) processes, after the individual semiconductor devices have been formed on the wafer.
These interconnects are typically fabricated using an additive damascene process in which an underlying insulating layer (e.g., silicon oxide) is patterned with open trenches. A subsequent deposition of a conductive metal on the insulating layer fills the trenches with metal. The metal is removed to the top of the insulating layer, but remains within the trenches to form a patterned conductor. Successive layers of insulator and metal are formed according to this damascene process, resulting in a multilayer metal interconnect structure.